A Methodology for Power-Aware Pipelining Via High-Level Performance Model Evaluations

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
With the ever growing demand for media-rich data intensive applications, the need to push for high performance, yet low power solutions is ever more present. Recent studies have shown previously, Chip Multi-Processors (CMPs) are ideal platforms for applications with high levels of parallelism. Examples of such applications are multimedia applications such as JPEG2000 and H.264. As application designers move towards chip-multiprocessor systems leaving the old high performance uniprocessor domain, new challenges arise. Among these challenges, one of the most difficult tasks is how to map an application onto a multicore system. During the application mapping process, task scheduling, and data allocation are two of the most critical steps.

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