A Modified Architecture Design for Advance Encryption Standard with Enhancement in Mix Columns for Secure Data Usage
In earlier days, Data Encryption Standard (DES) was considered as encryption standard with symmetrical key encryption with the key size of 56 bits. After certain days 56 bit key was considered to be small and for high data bit systems require key and data size to be large. In this paper, the authors are presenting an encryption algorithm called Advance Encryption Standard (AES). They have designed AES algorithm using Verilog HDL and in this design they have used look up table substitution for byte in state matrix, also for low complexity and low latency hardware for efficient performance. This design was simulated in Xilins ISE 13.2, compared results with previous design performances.