A Monitor Interconnect and Support Subsystem for Multicore Processors

Provided by: edaa
Topic: Hardware
Format: PDF
In many current SoCs, the architectural interface to on-chip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a separate low overhead subsystem for monitors is described. A key aspect of this approach is an on-chip interconnects specifically designed for monitor data with different priority levels. The efficiency of the people monitor interconnect is assessed for a multicore system using both interconnect and a system-level simulator.

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