A New Algorithm for FIR Digital Filter Synthesis for a Set of Fixed Coefficients
A new algorithm considering reduced adder graph technique for a set of fixed coefficients is presented. The reduced adder graph technique is beneficial in many filter applications such as FIR or IIR Filters, where the multipliers can be grouped in multiplier blocks. Multiplier block consists of additions, subtractions and shift operations. The multiplier block is used to implement a parallel multiplication of a variable x with a set of fixed coefficients. Generation of the minimal cost multiplier block from a set of fixed coefficients is known as the Multiple Constant Multiplication (MCM) problems. The complexity of digital Finite Impulse Response (FIR) filters is dictated by the number of adders/sub-tractors to implement the coefficient multipliers.