A New Architecture for Multiple-Precision Floating-Point Multiply-Add Fused Unit Design

Provided by: National University of Defense Technology
Topic: Hardware
Format: PDF
The floating-point Multiply-Add Fused (MAF) unit sets a new trend in the processor design to speed up floating point performance in scientific and multimedia applications. This paper proposes a new architecture for the MAF unit that supports multiple IEEE precisions multiply-add operation (A × B + C) with Single Instruction Multiple Data (SIMD) feature. The proposed MAF unit can perform either one double-precision or two parallel single-precision operations using about 18% more hardware than a conventional double-precision MAF unit and with 9% increase in delay.

Find By Topic