Academic Research Online Publisher
In this paper, the authors present a novel technique to design and optimize an ultra-low-voltage, ultra-low power CMOS Miler (OTA) using Particle Swarm Optimization (PSO). Advantages of this design are very small occupied area by transistors and low power consumption compare to other circuits. The values of width of transistors are taken as design parameters and total transistors area is taken as Cost Function (CF) to be minimized by PSO. The used topology was gate driven and DC level shifter that all transistors work in weak inversion.