A New Family of High-Performance Parallel Decimal Multipliers

Provided by: University of Santiago de Compostela
Topic: Hardware
Format: PDF
In this paper, the authors introduce two novel architectures for parallel decimal multipliers. Their multipliers are based on a new algorithm for decimal carry - save multioperand addition that uses a novel BCD - 4221 recoding for decimal digits. It significantly improves the area and latency of the partial product reduction tree with respect to previous proposals. They also present three schemes for fast and efficient generation of partial products in parallel. The recoding of the BCD - 8421 multiplier operand into minimally redundant signed - digit radix - 10, radix - 4 and radix - 5 representations using new re-coders reduces the complexity of partial product generation.

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