Provided by: IDOSI
In this paper, the authors present a new low power full adder based on a new logic approach, which reduces power consumption by implementing full adder using only one XOR module. In addition, output inverters have been embedded in the full adder cell, which boost driving capability, reduce delay and provide complementary outputs. Simulation has been carried out by HSPICE in 0.18 um bulk technology at 1.8V supply voltage. The results show that the proposed circuit has less power and PDP than recently proposed full adders in the literature.