A New High Precision Dynamic Comparator for Low Power High Speed ADCs

Provided by: International Journal of Engineering Trends and Technology
Topic: Hardware
Format: PDF
A novel dynamic comparator for low power and high speed analog-to-digital applications has been designed. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level, which is same as that of conventional comparators but the gain preceding the regenerative latch stage was improved and the complementary version of the output-latch stage, which has bigger output drive current capability at the same area. The schematics of existing dynamic comparators and proposed comparator are captured using Tanner tools schematic editor and simulated in 90nm PTM technology using HSPICE.

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