A New High Speed Low Power Performance of 8- Bit Parallel Multiplier-Accumulator Using Modified Radix-2 Booth Encoded Algorithm

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Provided by: International Journal of Latest Trends in Engineering and Technology (IJLTET)
Topic: Hardware
Format: PDF
There are different entities that one would like to optimize when designing a VLSI circuit. These entities can often not be optimized simultaneously, only improve one entity at the expense of one or more others. The design of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Power dissipation is recognized as a critical parameter in modern VLSI field. In Very Large Scale Integration (VLSI), low power VLSI design is necessary to meet MOORE 'S law and to produce consumer electronics with more back up and less processing systems.
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