A New Implementation of CMOS Full-Adders for Energy-Efficient Arithmetic Applications

The authors present two high-speed and low-power full adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced Power-Delay Product (PDP). They carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18 m CMOS technology, and were tested using a comprehensive test bench that allowed to measure the current taken from the full adder inputs, besides the current provided from the power supply.

Provided by: Creative Commons Topic: Hardware Date Added: Jul 2013 Format: PDF

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