Provided by: International Journal of Computer Science Engineering and Technology
Date Added: Mar 2014
In this paper, the authors present a novel low-power and high-speed 1-bit full-adder, which is designed based on pass transistor and TG logics. The main advantage of this design is low propagation delay and low-power consumption, which leads to achieving lower PDP than others. Intensive HSPICE simulation shows that the new full-adder consumes around 28.5% less power than 14T adder; moreover its PDP is 30% less than SS16T full-adder. They have compared two full-adders, 14T and SS16T, with their proposed full-adder.