Multipliers are one of the most important building blocks in processors. This paper describes a low-power 32Ã—32-bit parallel multiplier, designed and fabricated using a 0.13 Um double-metal double-poly CMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor logic circuits, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial-product generator and the partial-product addition circuitry have been proposed, simulated and fabricated. An efficient radix-2 recoding logic generates the partial products.