A New Parallel Counter Architecture with Reduced Transistor Count for Power and Area Optimization

Provided by: Creative Commons
Topic: Hardware
Format: PDF
Parallel counter achieved a high reputation through a novel pipeline partitioning methodology based parallel counter architecture which is made of less area & less power by reducing the number of transistor required for building the counter architecture. In this paper, a novel technique is proposed based on the comparison between conventional conditional data mapping flip-flop which is replacing the conventional 24 transistor flip-flop which is the basic building block of the parallel counter architecture. As it is a parallel counter architecture & it utilizes the state look-a-head logic it will counts 2 states per cycle through which they are achieving parallel working.

Find By Topic