A New Reduced Clock Power Flip-Flop for Future SOC Applications

In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D Flip Flop (CPSFF) here the authors are checking the working of CDMFF and the conventional D Flip-flop. Due to the immense growth in nanometer technology the SOC is became the future concept of the modern electronics the number of clock transistors are also considerably increased. In this paper, they propose a new system which will considerably reduce the number of transistor which will lead to the reduction in clocking power which will improve the overall power consumption.

Provided by: IJCTT-International Journal of Computer Trends and Technology Topic: Hardware Date Added: Aug 2012 Format: PDF

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