North Dakota State University
In this paper, the authors propose a new circuit level reliability evaluation methodology. The proposed methodology is based on a divide and conquer approach, which enjoys the benefits of device level accuracy and of block level efficiency. At the core of the reliability estimation engine lies a Monte Carlo algorithm which works with failure times modeled as Weibull and lognormal distributions for major wearout mechanisms: time dependent dielectric break down, negative bias temperature instability, electromigration, thermal cycling, and stress migration. As a case study, they demonstrate how the proposed reliability evaluation technique can be applied to a Network-on-Chip (NoC) router to identify the most vulnerable subblocks, which represent the reliability bottlenecks of the router.