A New Router Architecture for High-Performance Intrachip Networks
For almost a decade now, Network-on-Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex System-on-Chips (SoCs). A considerable number of NoC proposals are available, focusing on different sets of optimization aspects, related to specific classes of applications. Each such application employs a NoC as part of its underlying implementation infrastructure. Many of the mentioned optimization aspects target results such as Quality-of-Service (QoS) achievement and/or power consumption reduction.