A Novel 3 Transistor XOR Gate Based Full Adder Design for VLSI Applications

In this paper, the authors deal with a new way of designing XOR gate using 3 transistors. A full adder circuit has been designed using proposed 3T XOR circuit and a transmission gate is used extensively in Very Large-Scale Integration (VLSI) application. The power consumption of the circuit is in range of 421.7256uw to 581.542uw in 0.35 um technology with a voltage supply range of 1.8V to 3.3V. The simulation process has performed by the SPICE and DSCH tool based on TSMC 0.35um CMOS technology.

Provided by: International Journal of Research and Applications (IJRA) Topic: Hardware Date Added: Dec 2014 Format: PDF

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