A Novel Analysis on Low-Power High-Performance Flip-Flops

Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
The fast growth of the power density in integrated circuits has made area and power dissipation as the vital design measures. In this paper, several different flip-flop topologies are analyzed and an area and power efficient flip-flop design is proposed. This design overcomes the power dissipation due to the large pre-charge node capacitance, with reduced number of transistors. The comparative power analysis and performance improvements indicate that the proposed design is suitable for high-performance digital designs where the area and power dissipation is of major concern.

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