A Novel Approach for Design of Pulse Triggered Flip-Flop to Enhance Speed and Power

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Provided by: Auricle Technologies
Topic: Hardware
Format: PDF
In VLSI technology, flip-flops contribute a significant portion of chip area and power consumption to overall system design. Pulse triggered Flip-Flops (P-FFs) have single latch and hence simpler in circuit complexity. Use of explicit type design for P-FF gives the speed advantage. This paper presents various Pulse triggered Flip-flop (P-FF) designs and various techniques to achieve a better design in terms of power consumption and speed. Introduction of simple pass transistor in latch design can be used to speed up data transition.
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