A Novel Approach for High Speed and Low Power 4-Bit Multiplier
A circuit design for a new high speed and low power 4-bit braun multiplier is presented. The multiplier is implemented by using different power reduction techniques. To design a multiplier it is necessary to design an AND gate and full adder circuit using the power reduction techniques is presented. The design uses CMOS digital circuits in order to reduce the power dissipation while maintaining computational throughput. This paper presents an accurate method of simulating the power dissipation, delay and power delay product, using different techniques in 250nm technology with supply voltage is 2.5v.