A Novel Approach to Built an Area Efficient Architecture for Block LDPC Codes
Low Density Parity Checker (LDPC) decoder requires large amount of memory access which leads to high energy consumption. The amount of achievable memory bypassing depends on the decoding orders of the layers. The proposed decoder was implemented in TSMC 0.18m CMOS process. Experimental results show that for a LDPC decoder targeting IEEE 802.11n specification, the amount of memory access values can be reduced by 12.9% to 19.3% compared with the state-of-the-art design. At the same time, 95.6% to 100% hardware utilization rate is achieved.