A Novel Architecture of SRAM Cell for Low-Power Application

Provided by: IRD India
Topic: Hardware
Format: PDF
Low-power Random Access Memory (RAM) has seen a remarkable and rapid progress in power reduction. Many circuit techniques for active and standby power reduction in static and dynamic RAMS have been devised. This paper presents a new Static Random Access Memory (SRAM) cell. The proposed SRAM cell uses two trapezoidal-wave pulses and resembles behavior of static CMOS 4T-SRAM. The elementary cell structure of proposed SRAM cell consists of two high load resistors which are constructed of PMOS, and NMOS switch which is necessary to restrict short circuit current.

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