Provided by: International Journal of Engineering Trends and Technology
In this paper, the authors propose a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficient to achieve complete coverage of stuck-at faults, since these weights are sufficient to reproduce any specific test pattern. For sequential circuits, the weights they use are defined based on subsequences of a deterministic test sequence. Such weights allow them to reproduce parts of the test sequence and help ensure that complete fault coverage would be obtained by the weighted test sequences generated.