A Novel Design for High Speed-Low Power Truncation Error Tolerant Adder

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Provided by: Institute for Innovation in Science & Technology (IIST)
Topic: Hardware
Format: PDF
Now-a-days, in modern VLSI technology different kinds of errors are invitable. A new type of adder i.e. Error Tolerant Adder (ETA) is proposed to tolerate those errors and to attain low power consumption and high speed performance in DSP systems. In conventional adder circuit, delay is mainly certified to the carry propagation chain along the critical path, from the LSB to MSB. If the carry propagation can be eliminated by the technique proposed in this paper, a great improvement in speed performance and power consumption is achieved.
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