A Novel Design of All Digital Phase Locked Loop for VLSI Applications

Provided by: IRD India
Topic: Hardware
Format: PDF
The design of the ADPLL must intend to have a phase detection system with higher phase accuracy for minimum phase error. The need for All Digital Phase Locked Loop (ADPLL) was required basically because the microprocessors do not have enough processing power at such high frequencies even though with integrated Analog to Digital Converters (ADCs) and Digital to Analog Converters (DACs). In this paper, implementation of ADPLL is described in detail. Its simulation results using Xilinx are also discussed.

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