A Novel DRAM Architecture as a Low Leakage Alternative for SRAM Caches in a 3D Interconnect Context
In this paper the authors present a DRAM architecture that improves the DRAM performance/power trade-off to increase their usability on low power chip design using 3D interconnects technology. The use of a finer matrix subdivision and buffering the bitline signal at the local-block level allows to reduce both the energy per access and the access time. The obtained performances match those of a typical low power SRAM, while achieving a significant area and static power reduction compared to these memories. The 128 kb memory architecture proposed here achieves an access time of 1.3 ns for a dynamic energy of less than 0.2 pJ per bit.