International Journal of Engineering Research and Development (IJERD)
Duet advancement of new technology in the field of VLSI and embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Sever a ladder architecture designs have been developed to increase the efficiency of the adder. In this paper, the authors introduce an architecture that performs high speed modified carry select adder using Binary to Excess-1 Converter (BEC) technique.