Imperial College London
In this paper, the authors concern with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, they investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximize the performance of a set of DSP benchmark applications, given a fixed silicon budget. They extend their previous mathematical programming framework by proposing a novel set of heuristics, capable of providing upper-bounds on the achievable reconfigurable-to-fixed-logic performance ratio. Moreover, they use linear-programming bounding procedures from the operations research community to provide lower-bounds on the same quantity.