Provided by: Institute of Electrical & Electronic Engineers
Date Added: Jan 2010
In this paper, the authors present a novel Context Modeling (CM) architecture used in JPEG2000 encoder targeting next generation of cameras. The implementation is based on a newly emerging coarse-grained Dynamically Reconfigurable (DR) processor. A novel partial parallel architecture for the CM is introduced which can be easily tailored for the target DR processor in order to achieve higher performance results. Simulation results show that the resulting architecture provides throughput reaching up to 60.82MS/s, representing 1.2 x speed-ups compared to previous parallel CM architectures.