A Novel High Performance Implementation of 64 Bit MAC Units and Their Delay Comparison
A novel high performance 64 bit Multiplier-and-ACcumulator (MAC) is implemented in this paper. MAC plays a vital role in most of the Digital Signal Processing (DSP). The MAC unit is designed using vedic, braun, dadda multiplier and carry save adder hence, compared with performance of MAC unit using Wallace multiplier and carry save adder. In gate level Verilog hdl used for coding digital circuits using tool Xilinx ISE 10.1i and target family Spartan 3E,Device-XC3S500,speed -5,package: FG320. The synthesized for the proposed digital circuits.