International Journal of Computer Applications
In any integrated circuit, power consumption plays a paramount role and is considered as one of the top challenges in international technology roadmap for semiconductors. In this paper, a low power circuit designed to operate in sub-threshold region is proposed. Voltage scaling technique is incorporated to reduce dynamic power consumption while static or leakage power is greatly reduced with forced stack technique. The present technique VS-Stack features very low power dissipation as compared to its standard CMOS counterparts in sub-threshold region.