A Novel Low-Power A2 Adder Scheme Based on Reduced Transistor Count Full-Adder Cells

Provided by: International Journal of Electronics and Computer Science Engineering
Topic: Hardware
Format: PDF
A power-efficient 8-bits digital adder using the new arithmetic A2 redundant binary representation is presented. This structure is very suitable for implementation in VLSI of mixed-signal circuits built around Multiplier Digital to Analog Converter (MDAC) cells. Using a reduced transistor count full-adder cells shows that the authors' approach significantly reduces the power consumption of such adders compared to the classical scheme using classical full-adder cells. The adder being studied was optimized for power efficiency at 0.18μm CMOS process.

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