A Novel Low Power Optimization for On-Chip Interconnection

Provided by: International Journal of Scientific and Research Publication (IJSRP)
Topic: Hardware
Format: PDF
In various circuit modules, transmitting signals over large areas required long inter-connections. With the continuous scaling of technology and increased die area, cross sectional areas of wires has been scaled down while interconnect length and frequency has increased. In the damping factor and the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of signals across the line are the two figure of merits that were studied and a primary result of this paper is that a range for the length of the interconnect exists for which inductance effects are prominent and under certain conditions, the inductance effects are negligible.

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