Institute of Electrical & Electronic Engineers
Shrinking silicon technologies, increasing logic densities and clock frequencies on FPGA (Field Programmable Gate Array) lead to rapid elevation in power density, which are translated to higher on-chip temperature. Recently, the FPGA industry (e.g. Xilinx, Altera) recognized the dominance of the heat problem as one of its key design issues, which should be tackled immediately. In this paper, considering a novel temperature-aware placement and routing algorithm, a systematic methodology to achieve a more "Balanced" temperature distribution in the whole FPGA device, is introduced.