A Novel Optimized JTAG Interface Circuit Design
In this paper, the authors describe a novel optimized JTAG interface circuit between a JTAG controllers and target IC. Being able to access JTAG using only one or two pins, this circuit does not change the original boundary scanning test frequency of target IC. Compared with the traditional JTAG interface which based on IEEE std. 1149.1, this reduced pin technology is more applicability in pin limited devices, and it is easier to control the scale of target IC for the designer.