A Novel Power Reduction Technique for CMOS Circuits Using Voltage Scaling and Transistor Gating

Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
The colossal portion of power in CMOS circuits is consumed during switching which is termed as dynamic power consumption. This absorbs more than 60% of the overall power in the circuit. However, as the technology scales down, sub-threshold leakage becomes commensurable to dynamic power dissipation. This happens as a result of reduction in threshold voltage and device geometry. In this paper, a high performance and power efficient technique is proffered which operates in sub-threshold region.

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