A Novel Vedic Divider Architecture with Reduced Delay for VLSI Applications

Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
The ever increasing demand in VLSI architecture to handle complex systems has resulted for designing of high speed divider architecture. The divider is designed using ever known ancient methodology "Vedic mathematics". There are several methods present in Vedic mathematics but here Parvartya sutra is used. It is a general division formula which can be applicable to all cases of division which is an efficient way for dividing large numbers with respect to delay and power consumption. Here, thirty-two bit divider architecture is implemented using this sutra and synthesized and simulated using Xilinx ISE simulator and implemented on virtex-4 FPGA device XC4VLX15.

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