A Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 Compressor

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Provided by: International Journal of Engineering Research and Development (IJERD)
Topic: Hardware
Format: PDF
With the appearance of new innovation in the fields of VLSI and correspondence, there is likewise a perpetually developing interest for fast transforming and low range outline. It is likewise a remarkable certainty that the multiplier unit structures a fundamental piece of processor configuration. Because of this respect, rapid multiplier architectures turn into the need of the day. In this paper, the authors acquaint a novel structural engineering with perform high velocity duplication utilizing old Vedic math's strategies.
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