A Parallel Architecture for Secure FPGA Symmetric Encryption

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Provided by: Pennsylvania State Employees Credit Union
Topic: Hardware
Format: PDF
Cryptographic algorithms are at the heart of secure systems worldwide, providing encryption for millions of sensitive financial, government, and private transactions daily. Reconfigurable computing platforms like FPGAs provide a relatively low-cost, high-performance method of implementing cryptographic primitives. Several standard algorithms are used: the Data Encryption Standard (DES), its cipher block chained counterpart and the Advanced Encryption Standard (AES). Conventional high-performance architectures utilize loop-unrolled approaches where internal hardware functions are duplicated. The authors propose a parallel architecture in which internal hardware functionality is not duplicated but reused.
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