Provided by: Ferdowsi University Of Mashhad
Date Added: Apr 2013
In this paper, the authors present design and implementation of a general parallel high speed architecture for digital Fuzzy Logic Controller (FLC). The proposed design is in structural level in which adder, multiplier, and divider used in FLC have Fine-Grain multiplexer based pipelined array structure. Simulations were carried out by using DSP builder in MATLAB/Simulink and the architecture has been successfully synthesized and implemented using Quartus II 9.1and StratixII FPGA for a 2- input 1-output FLC, with 8 rules and maximum clock rate of 301.84MHz.