A Parallel Sort Engine With Dynamic Memory for a Multiprocessor-on-a-Chip

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Provided by: University of Calgary
Topic: Hardware
Format: PDF
The authors have recently developed MaRS a reconfigurable heterogeneous computing engine, targeting multimedia data processing and wireless communication. They propose a custom-designed alternative to a memory system (generated by a memory generator) used in a 4K-word sorting accelerator which improves area efficiency by some 20%. They also show how the control unit is dramatically simplified with this new memory comparing with the sophisticated memory controller in the previous version. Furthermore, since the memory introduced here is custom designed, its size is tailored to any specific need.
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