A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor

Provided by: SERC
Topic: Hardware
Format: PDF
Previous papers have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, they developed a detailed Petri net model of IP forwarding application on IXP2400 that models the different levels of the memory hierarchy. The cell based interface used to receive and transmit packets in a network processor, leads to some small size DRAM accesses. Such narrow accesses to the DRAM expose the bank access latency, reducing the bandwidth that can be realized.

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