A Physical-Level Study of the Compacted Matrix Instruction Scheduler for Dynamically Scheduled Superscalar Processors

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Provided by: University of Toledo
Topic: Data Centers
Format: PDF
In this paper, the authors study hardware complexity (physical level characteristics) of the recently proposed compacted matrix instruction scheduler for dynamically scheduled, superscalar processors. Previous paper focused on the matrix scheduler's architecture and argued in support of its speed and scalability advantages; however, neither actual physical-level investigations nor models were reported for it. Using full-custom layouts in a commercial 90 nm fabrication technology, this paper investigates the latency and energy variations of the compacted matrix and its accompanying logic as a function of the issue width, the window size and the number of global checkpoints.
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