A Pipelined Architecture for High Throughput Efficient Turbo Decoder
This paper presents a new pipelined architecture of Turbo decoder which runs at nearly four times the speed of a recently reported architecture with a reasonable increase in hardware. The proposed architecture is based on block-interleaved pipelining technique which enables the pipelining of the Add-Compare-Select-Offset (ACSO) kernels. Moreover Next Iteration Initialization (NII) method has been adapted in the proposed work to initialize sliding window border values. The decoder chip consumes 219.8 mW of power at a maximum operating frequency of 192.3 MHz when implemented using 0.18 ?m CMOS technology.