A Pipelined Asynchronous Cache System

Provided by: National Science Foundation
Topic: Hardware
Format: PDF
In this paper, the authors present the design of a pipelined cache system for use in an asynchronous MIPS R3000-compatible processor. Although caches have been used in a few asynchronous processors (AMULET2e, TITAC-2), these rely on timing assumptions and delay matching or differ little from conventional synchronous designs. Their cache is designed as a distributed message passing system and implemented with full-custom quasi delay-insensitive circuits. This design achieves timing robustness, low latency, and high average-case throughput by making minimal assumptions on signal delays.

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