Institute of Electrical & Electronic Engineers
Multimedia applications, and in particular the encoding and decoding of standard image and video formats, are usually a typical target for System-on-Chip (SoC). The Two-Dimensional Discrete Cosine Transformation (2D-DCT) is a commonly used frequency transformation in graphic compression algorithms. Many hardware implementations, adopting disparate algorithms, have been proposed for Field Programmable Gate Arrays (FPGA). These designs focus either on performance or area, and often do not succeed in balancing the two aspects. In this paper, the authors present a design of a fast 2DDCT hardware accelerator for a FPGA-based SoC.