A Power-aware Hybrid RAM-CAM Renaming Mechanism for Fast Recovery

Provided by: Universidad Politecnica de Madrid
Topic: Hardware
Format: PDF
Modern superscalar processors implement register renaming by using either RAM or CAM tables. The design of these structures should address their access time and misprediction recovery penalty. While direct-mapped RAMs provide faster access times, CAMs are more appropriate to avoid recovery penalties. Although they are more complex and slower, CAMs usually match the processor cycle in current designs. However, they do not scale with the number of physical registers and the pipeline width. In this paper, the authors present a new hybrid RAM-CAM register renaming scheme, which combines the best of both approaches.

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