A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
IR drops in a Power Delivery Network (PDN) on Chip Multi-Processors (CMPs) can worsen the quality of voltage supply and thereby affect overall performance. This problem is more severe in 3D CMPs with Network-on-Chip (NoC) fabrics where the current in the PDN increases proportionally to the number of device layers. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent; for instance, each new core mapping on the 3D die will change traffic patterns and have a unique distribution of IR-drops in the PDN.
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