A Power Efficient Linear Equation Solver on a Multi-FPGA Accelerator

Provided by: Utah Section PGA
Topic: Hardware
Format: PDF
In this paper, the authors present an approach to explore a commercial multi-FPGA system as high performance accelerator and the problem of solving a LU decomposed linear system of equations using forward and back substitution is addressed. Block-based right-hand-side solver algorithm is described and a novel data flow and memory architectures that can support arbitrary data types, block sizes, and matrix sizes is proposed. These architectures have been implemented on a multi-FPGA system. Capabilities of the accelerator system are pushed to its limits by implementing the problem for double precision complex floating-point data.

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